Field of the Invention
The invention relates to the reliability of an NAND or an NOR flash memory and a method for providing a flash memory with less reliability deterioration even a writing and an erasing operations are repeatedly performed.
Description of Related Art
FIG. 1 is a schematic cross-sectional diagram illustrating a structure of a cell array of an NAND flash memory. FIG. 2 is an equivalent circuit diagram of the cell array. An N well 12 is formed in a P-type silicon substrate 10. A P well 14 is formed in the N well 12. A plurality of transistors, which constitutes a NAND string, are formed on the P well 14. An NAND string includes a plurality of memory cells connected in serial, a source line selection transistor connected with one terminal of a memory cell and a bit line selection transistor connected with the other terminal. Referring to FIG. 1, each memory cell includes a control gate (word lines WL1, WL2 . . . WLn) 20, a selection gate 22 at the source line selection transistor, and a selection gate 24 at the bit line selection transistor. In the P well 14, a plurality of NAND strings are formed along a row direction, and the NAND strings in one P well 14 constitute a block.
A source line SL is electrically connected to an n-diffusion region (a source region) 23 of the source line selection transistor, a bit line BL is electrically connected to an n-diffusion region (a drain region) 23 of the bit line selection transistor. Moreover, a p+ diffusion region 26 for a contact portion is formed in the P well 14, and an n+ diffusion region 27 is formed in the N well 12. The diffusion regions 26 and 27 are connected via a common contact portion 28 of the N well/P well. When an erasing operating is to be performed on the selected block, a high-voltage erase pulse is applied to the P well via the common contact portion 28, which will be described below.
Referring to FIG. 2, a plurality of word lines WL1, WL2 . . . WLn are formed along the row direction crossing with the NAND strings, and the word lines WL are connected in common to the control gate 20 of the corresponding memory cell in the row direction. The selection gate lines SGS are connected in common to the selection gate 22 of the source line selection transistor in the row direction. The selection gate lines DSG are connected in common to the selection gate 24 of the bit line selection transistor in the row direction. When the source line selection transistor is conducted via the selection gate lines SGS, the NAND strings are electrically connected to a source line SL, and when the bit line selection transistor is conducted via the selection gate lines DSG, the NAND strings are electrically connected to a bit line BL.
FIG. 3 is a graph illustrating voltage waveforms of each node in the block selected to be erased when the erasing operation is performed on the NAND flash memory. A node N1 represents a waveform of the common contact portion 28 of the N well/P well, N2 represents a waveform of the diffusion region 23 used by the contact portion of the source line SL, N3 represents a waveform of the selection gate 22 of the source line selection transistor, N4 represents a waveform of the word lines (the control gate) 20 in the same block, N5 represents a waveform of the selection gate 24 of the bit line selection transistor, and N6 represents a waveform of the diffusion region used by the contact portion of the bit line BL. Furthermore, in a non-selected block, N4 has a waveform in the same manner as N3 or N5 in the block selected to be erased.
In the NAND flash memory, the data erasing operation is performed by a block unit. At this time, word lines in the selected block are set to 0 V or a voltage lower than a voltage of the P well, the P well 14 forming the memory cell array is applied with an erase pulse Ps having a strip-type positive voltage, and after the erase pulse Ps is applied, the potential of the P well 14 returns to 0 V. In this case, each of the nodes N2, N3, N5 and N6 is boosted by a capacitive coupling effect with the P well 14. After the erasing operation is performed, whether a threshold of each memory cell in the selected block is under a specific value is determined through a verify-read operation. If the threshold of each cell in the block is under the specific value, the erasing operation is completed; however, if the threshold of a part of the cells is over the specific value, the erase pulse Ps is applied again and perform the verify-read operation (e.g., see Patent document 1).
During a writing operation, the P well 14 is set to 0 V, and a high voltage is applied to a selected word line. The bit line BL is applied with 0 V or a positive potential. In a scenario of applying 0 V, a silicon surface of the selected cell has 0 V and a tunnel current of the electrons flowing from the silicon substrate toward the floating gate is generated. Thereby, the threshold of the cells becomes higher than the specific value.
In the NAND flash memory, a memory cell array in a three-dimensional form is proposed in order to improve the degree of integration (see non-patent literatures 1, 2 and 3). For instance, a poly silicon pillar serving as the channel region are formed from the silicon substrate in a vertical direction, and a plurality of control gates are formed along the poly silicon pillar. A layer for accumulating charges is formed between the control gates and the channel portion.